1. Field of the Invention
The present invention relates to electronic circuits and, in particular, to a comparator circuit that utilizes cascaded differential amplifiers for increased gain and speed performance plus a simple, one element hysteresis circuit.
2. Discussion of the Prior Art
A comparator is essentially a differential amplifier running open loop so that there is a considerable amount of amplification. Hysteresis is often added to comparator circuits to prevent the output from changing state as a result of noise fluctuations on the differential inputs.
For example, U.S. Pat. No. 4,670,671, issued June 2, 1987 to De Weck, discloses a CMOS comparator which uses an input differential stage having feedback current mirror loads that provide high speed current signals to an output cascode stage. The current mirror arrangement provides fast signal propagation through the comparator. Hysteresis is established by the output of the comparator being positively fedback through a similar feedback differential stage, thus superimposing controlled current signals into the cascode stage. Hysteresis of the output signal with respect to a differential input signal is controlled by the ratio of biased currents of internal current sources.
U.S. Pat. No. 4,110,641, issued Aug. 29, 1978, to Payne, discloses a CMOS voltage comparator with internal positive current feedback to achieve hysteresis. The voltage level at which the switching occurs is precisely setable. Hysteresis is introduced such that when the set voltage level is exceeded, the output switches quickly and remains in that state until the input voltage drops by a predetermined hysteresis voltage.
U.S. Pat. No. 4,485,312 issued Nov. 27, 1984, to Kusakabe et al, discloses a hysteresis circuit in which a differential pair of transistors is provided for voltage comparison. A bias circuit for setting a reference voltage is connected to the base of one of the differential pair. A second differential pair is provided for reference voltage switching. The transistors of the second differential pair have their bases connected to the collectors of the transistors of the first differential pair as well as to the biased circuit in a positive feedback relationship.
Each of the above-mentioned circuits implements hysteresis either with an additional differential "bleeder" network or with a complicated feedback arrangement around the output stage. Thus, these designs suffer from a number of disadvantages. First, a large number of additional circuit elements are required. Second, critical matching is required among certain circuit elements. Third, the complex convoluted layouts required to implement these designs exhibit attendant increases in parasitic loads. Also, these circuits exhibit reduced switching speed and longer settling times due to the reduced available switching current and parasitic loading.